1. Field of the Invention
The present invention relates to a clock signal phase comparator, and more particularly to an improved clock signal phase comparator employed in a phase control system and capable of decreasing current consumption in the phase control system by partially or entirely disabling the phase control system when a phase-locked clock signal is detected.
2. Description of the Prior Art
As shown in FIG. 1, a clock signal phase comparator according to the conventional art includes a phase detector 10 which compare a clock signal CLKin to a reference clock signal CLKfbk that results from feedback via a voltage controlled oscillator (not shown), and which outputs a high or low level output signal OUT to a phase control system (not shown).
With reference to FIG. 2, the phase detector 10 includes: a NAND gate N1 for NANDing the base clock signal CLKfbk and a supply voltage signal VDD; a NAND gate N2 for NANDing an output signal of the NAND gate N1 and the clock signal CLKin and for outputting the resultant signal to a node ND2; a NAND gate N3 for NANDing the output signal from the NAND gate N1 and another input signal; a NAND gate N4 for NANDing the output signal of the NAND gate N3 and the clock signal CLKin, and for outputting the resultant signal to a node ND1; a NAND gate N5 for NANDing the output signals from NAND gate N2 and NAND gate N6; a NAND gate N6 for NANDing the output signal of the NAND gate N4 and the output signal of the NAND gate N5; an inverter I1 for inverting the clock signal CLKin; a pulse signal generator 10a for generating a pulse signal in accordance with the output signal of the inverter I1; a NAND gate N7 for NANDing the output signal of the pulse signal generator 10a and the output signal of the NAND gate N6; and an inverter I2 for inverting the output signal of the NAND gate N7 and for outputting the output signal OUT.
The output terminal of the NAND gate N2 is connected to an input terminal of the NAND gate N1. The output terminal of the NAND gate N4 is connected to an input terminal of the NAND gate N3. The NAND gate N5 NANDs the respective output signals of the NAND gate N2 and the NAND gate N6.
The operation of the thusly constituted phase detector 10 will now be described with reference to the accompanying drawings.
The phase detector 10 compares the reference clock signal CLKfbk as shown in FIG. 3 and the clock signal CLKin as shown in FIG. 3. Thus when the reference clock signal CLKfbk starts faster than the clock signal CLKin, the output signal OUT becomes a low level. By contrast when the clock signal CLKin starts faster than the reference clock signal CLKfbk, the output signal OUT becomes a high level.
With reference to FIGS. 2 and 3A-3C, when the reference clock signal CLKfbk obtains a high level while the clock signal CLKin retains in a low level, a high level signal occurs at the node ND1 and a low level signal occurs at the node ND2. The NAND gate N7 outputs a high level signal and the inverter I2 outputs a low level signal serving as the output signal OUT, whereby the clock signal CLKin is regarded as starting slower than the reference clock signal CLKfbk. On the other hand, when the reference clock signal CLKfbk has a low level and the clock signal CLKin has a high level, the node ND1 comes to have a low level signal and the node ND2 comes to have a high level signal, as shown in FIG. 2. At this time, the pulse signal generator 10a which received a high level signal via the inverter I1, applies a high level signal to the NAND gate N7. Therefore, the NAND gate N7 outputs a low level signal, and the inverter I2 outputs a high level signal serving as the output signal OUT, whereby the clock signal CLKin comes to start faster than the reference clock signal CLKfbk.
However, because the conventional clock phase comparator simply compares each start time of the clock signal CLKin and the reference clock signal CLKfbk, when the clock signal CLKin and the reference clock signal CLKfbk are locked, the phase control system is alternately carried out in a faster mode or a slower mode. Therefore, the phase control system requires an otherwise unnecessary electric power, for further increasing power consumption even in a stand-by state.